1. Field of Invention
The present invention relates to a tri-state buffer circuit that is used for an output buffer circuit of a semiconductor integrated circuit, and more particularly to a tri-state buffer circuit that is suitable for high integration of semiconductor integrated circuits.
2. Description of Related Art
A tri-state buffer circuit is a buffer circuit that outputs one of three possible states. Among the three states, two of them are low impedance states, one of which is at high level and the other of which is at low level. The remaining one is a high impedance state. The tri-state buffer circuit is used, for example, when outputs of a plurality of logical circuits are transferred on one signal line.
FIG. 4 shows a circuit diagram of the configuration of a conventional tri-state buffer circuit. As shown in FIG. 4, the tri-state buffer circuit includes a P-channel transistor QP11 and an N-channel transistor QN11 that invert an input signal IN that is applied to a data input terminal 1 and output the inverted signal as an output signal OUT from a data output terminal 3, a P-channel transistor QP12 that is serially connected to the transistor QP11, an N-channel transistor QN12 that is serially connected to the transistor QN11, and an inverter circuit 11 that inverts a control signal {overscore (OE)} and outputs a control signal OE.
The transistor QP12 performs switching between a first power supply voltage VDD and the transistor QP11 according to the control signal {overscore (OE)} that is applied to a control terminal 2. On the other hand, the transistor QN12 performs switching between the transistor QN11 and a second power supply voltage VSS (normally, a grounding potential) according to the control signal OE that is outputted from the inverter circuit 11.
Next, an operation of the conventional tri-state buffer circuit shown in FIG. 4 is described. The operation of the tri-state buffer circuit is categorized into the following three operations depending on the state of the input signal IN that is applied to the data input terminal 1 and the state of the control signal {overscore (OE)} that is applied to the control terminal 2. Each of the operations will be described below.
(1) A state in which the control signal {overscore (OE)} is at low level, and the input signal IN is at low level.
The control signal {overscore (OE)} at low level is supplied to a gate of the transistor QP12, thereby switching the transistor QP12 to an ON state. On the other hand, the inverter circuit 11 receives the control signal {overscore (OE)} at low level, inverts the control signal {overscore (OE)} and outputs a control signal OE at high level. The control signal OE at high level is supplied to a gate of the transistor QN12, which causes the transistor QN12 to switch to an ON state. Since the transistors QP12 and QN12 switch to an ON state, the transistors QP11 and QN11 operate as an inverter circuit, whereby the input signal IN at low level is inverted by the transistors QP11 and QN11, and an output signal OUT at high level is outputted from the data output terminal 3.
(2) A state in which the control signal {overscore (OE)} is at low level, and the input signal IN is at high level
Since the control signal {overscore (OE)} is at low level, the transistors QP12 and QN12 switch to an ON state, in a similar manner as in (1) above. As a result, the transistors QP11 and QN11 operate as an inverter circuit, whereby the input signal IN at high level is inverted by the transistors QP11 and QN11, and an output signal OUT at low level is outputted from the data output terminal 3.
(3) A state in which the control signal {overscore (OE)} is at high level
The control signal {overscore (OE)} at high level is supplied to the gate of the transistor QP12, thereby switching the transistor QP12 to an OFF state. On the other hand, the inverter circuit 11 receives the control signal {overscore (OE)} at high level, inverts the control signal {overscore (OE)} and outputs a control signal OE at low level. The control signal OE at low level is supplied to the gate of the transistor QN12, thereby switching the transistor QN12 to an OFF state. Since the transistors QP12 and QN12 switch to an OFF state, the data output terminal 3 is placed in a high impedance state regardless of the state of the transistors QP11 and QN11, in other words, regardless of the state of the input signal IN.
As described above, in the conventional tri-state buffer circuit, when the control signal {overscore (OE)} applied to the control terminal 2 is at low level, the data output terminal 3 outputs an output signal OUT having an inverted state of the input signal IN applied to the input terminal 1. Also, when the control signal {overscore (OE)} inputted to the control terminal 2 is at high level, the data output terminal 3 is always placed in a high impedance state regardless of the state of the input signal IN applied to the input terminal 1. In this manner, the conventional tri-state buffer circuit can output one of three states including low impedance states, one of which is at high level and the other of which is at low level, and a high impedance state.
FIG. 5 shows a circuit diagram of the configuration of the inverter circuit 11 that is used in the conventional tri-state buffer circuit shown in FIG. 4. The inverter circuit 11 includes a P-channel transistor QP3 and an N-channel transistor QN3. When a signal at low level is inputted to the gates of the transistors QP3 and QN3, the transistor QP3 switches to an ON state, and the transistor QN3 switches to an OFF state, which causes drains of the transistors QP3 and QN3 to output a signal at high level. On the other hand, when a signal at high level is inputted to the gates of the transistors QP3 and QN3, the transistor QP3 switches to an OFF state, and the transistor QN3 switches to an ON state, which causes the drains of the transistors QP3 and QN3 to output a signal at low level. In this manner, the inverter circuit 11 inverts the control signal {overscore (OE)} applied to the control terminal 2 and outputs the control signal OE.
FIG. 6 shows an example of a layout of the conventional ti-state buffer circuit shown in FIG. 4. As shown in FIG. 6, a semiconductor substrate includes therein a P-type impurity diffusion region 61 for the P-channel transistors QP11 and QP12 in the last stage, an N-type impurity diffusion region 62 for the N-channel transistors QN11 and QN12 in the last stage, a P-type impurity diffusion region 63 for the P-channel transistor QP3 of the inverter circuit, and an N-type impurity diffusion region 64 for the N-channel transistor QN3 of the inverter circuit.
A gate 65 of the transistors QP11 and QN11, a gate 66 of the transistor QP12, a gate 67 of the transistor QN12 and a gate 68 of the transistors QP3 and QN3 are formed of polycrystal silicon through a gate insulation layer over the semiconductor substrate where the impurity diffusion regions are formed. Furthermore, a first wiring layer including a first power supply wiring 71 and a second power supply wiring 72, and a second wiring layer including wirings between transistors are formed through an interlayer insulated layer. Openings are provided at specified sections of the interlayer insulated layer, in which portions of the first and second wiring layers are connected to the impurity diffusion regions, and other portions are connected to the polycrystal silicon.
Such a conventional tri-state buffer circuit needs a total of four transistors including two P-channel transistors and two N-channel transistors in the last stage. The current that flows in the last stage is substantially large, and therefore the sizes of the sources and drains of the four transistors need to be larger than the sizes of the sources and drains of normal transistors. For example, they may often become four times to ten times larger than the sizes of the sources and drains of the normal transistors. Moreover, a P-channel transistor has a transistor current amplification rate xcex2 lower than that of an N-channel transistor (for example, xcex2 of a P-channel transistor is about half that of an N-channel transistor), which requires a channel width that is about twice as large as that of the N-channel transistor in order to provide an output with an equal ON resistance.
Therefore, in the conventional tri-state buffer circuit shown in FIGS. 4xcx9c6, since two P-channel transistors of a larger size are needed in the last stage, the area occupied by these transistors in the semiconductor substrate increases, and this results in a problem in that a higher integration of a semiconductor integrated circuit is hindered. On the other hand, in recent years, much higher integration of semiconductor integrated circuits has become desirable.
In view of the problems described above, it is an object of the present invention to provide a smaller sized tri-state buffer circuit that can realize a high integration of a semiconductor integrated circuit.
To solve the problems described above, a tri-state buffer circuit in accordance with the present invention has an AND device that obtains a logical product of an input signal and a control signal, inverts the logical product and outputs the same; a P-channel transistor having a gate that is supplied with a signal outputted from the AND device and a source that is supplied with a first power supply voltage to output an output signal at the drain; a first N-channel transistor that is complementarily connected with the P-channel transistor, the first N-channel transistor having a gate that is supplied with a signal outputted from the AND device and a drain that outputs an output signal; and a second N-channel transistor connected between the first N-channel transistor and a second power supply voltage, wherein the second N-channel transistor has a gate that is supplied with the control signal and allows a current to flow from a source of the first N-channel transistor to the second power supply voltage according to the control signal.
The present invention is particularly effective when the size of source/drain of a P-channel transistor is four times or more greater than the size of source/drain of any of transistors used in the AND device. It is noted that the AND device may be a NAND circuit. Also, the tri-state buffer circuit may further include an inverter device that inverts an external control signal that is externally supplied, and outputs the inverted signal as the control signal.
In accordance with the present invention, the number of P-channel transistors that occupy a large area in a semiconductor substrate can be reduced from two as required in the conventional type to one, with the result that a tri-state buffer circuit having a smaller size than the conventional circuit can be realized.